1. Field of the Invention
This invention relates to the formation of an MOS device of an integrated circuit structures on semiconductor substrates. More particularly, this invention relates to a process for forming an MOS device using cobalt silicide both as a contact and as an implantation media for forming the source/drain regions and the doped gate electrode of the MOS device.
2. Description of the Related Art
In the formation of integrated circuit structure, and particularly in the formation of MOS devices using polysilicon gate electrodes, it has become the practice to provide a metal silicide layer or contact over the polysilicon gate electrode, and over the source/drain regions of the silicon substrate, to facilitate electrically and metallurgically connecting the silicon to metal interconnects. Thus, for example, a titanium metal layer is usually blanket deposited over the polysilicon gate electrode and the source/drain regions of the silicon substrate, as well as over the silicon oxide insulation regions of the substrate, e.g., the field oxide regions. The structure is then heated sufficiently to cause the titanium in contact with the silicon to react, thereby forming titanium silicide, e.g., heated to about 650.degree. C., while the titanium over the silicon oxide does not react. The unreacted titanium is then removed, leaving only titanium silicide over the silicon source/drain regions of the substrate and over the polysilicon gate electrode. The resulting titanium silicide is then further annealed at a higher temperature, e.g., about 700.degree.-800.degree. C., to convert the titanium silicide to a more electrically desirable (lower resistivity) phase.
However, as the sizes of integrated circuit structures have continued to become smaller and smaller, problems have arisen with the continued use of titanium silicide, particularly in the formation of narrow lines, because the less acceptable lower temperature phase of titanium silicide tends to predominate on narrower lines, apparently due to the failure of the lower temperature phase to convert to the low resistivity higher temperature titanium silicide phase when the line width approaches the grain size of the lower temperature phase. It has, however, been found that cobalt silicide (usually CoSi.sub.2) is not subject to the same phase problems when used in forming narrow lines.
While the substitution of cobalt silicide for titanium silicide thus solves some of the problems encountered with the use of titanium silicide with very narrow lines, other problems have, in turn, been encountered with this substitution. For example, when forming very shallow source/drain regions in a single crystal semiconductor substrate such as a silicon substrate by implantation, it is difficult to provide the desired control of the depth of the implantation directly into the substrate, thereby resulting in deeper junctions (causing more junction leakage), as well as possible channeling of the implanted dopant into the substrate. However, by forming the titanium silicide layer over the silicon substrate first, i.e., prior to the implantation step, the implantation depth may be controlled to implant the dopant into the titanium silicide layer instead of the underlying substrate. That is, the titanium silicide layer may be conveniently used as a media for the implantation of one or more dopants therein, due to its thicknesses relative to the thickness of the desired source/drain regions to be formed in the substrate. After the implantation step, diffusion of the dopant(s) from the implanted titanium silicide into the silicon substrate may be carried out during a subsequent anneal, resulting in the desired shallow source/drain regions.
However, when cobalt silicide is substituted for titanium silicide, for the reasons discussed above with respect to smaller line widths, problems are encountered with the concurrent use of the cobalt silicide as a media for implantation because the cobalt silicide has been found to form unevenly in thickness, particularly over raised portions of the underlying integrated circuit structure (such as the polysilicon gate electrode) where the edges of the cobalt silicide tend to thin. This is illustrated in the prior art structure of FIG. 1 wherein cobalt silicide contacts 14 and 16 are shown respectively formed over source/drain regions 4 and 6 in the region of silicon substrate 2 bounded by field oxide 8, and cobalt silicide gate contact 18 has been formed over a polysilicon gate electrode 12 and gate oxide 10 between source/drain regions 4 and 6. Oxide spacers 13 are shown conventionally formed on the sidewalls of gate electrode 12. FIG. 1 shows the thinning of cobalt silicide 18 layer at 19, adjacent the edges of the raised portion of gate electrode 12.
While Liu et al., in an article entitled "Mechanisms for Process-induced Leakage in Shallow Silicided Junctions", IEDM 86, pp 58-61, discusses that a semiconductor substrate may be implanted with dopant either before or after forming cobalt silicide thereon, there appears to be no recognition of any problems encountered with the use of cobalt silicide rather than titanium silicide during the implantation. That is, the above-described problem of thinning of the cobalt silicide at the edges of a raised gate electrode is not discussed by Liu et al. (perhaps because they were using a much thicker silicide which can be tolerated for less advanced process technologies).
The formation of cobalt silicide using a capping layer of titanium or titanium nitride formed over the cobalt layer has also been proposed to improve certain properties of the cobalt silicide subsequently formed over the substrate. For example, Berti et al., in an article entitled "A Manufacturable Process for the Formation of Self Aligned Cobalt Silicide in a Sub Micrometer CMOS Technology", published on pages 267-273 of the VMIC Conference held in Santa Clara, Calif. in 1992, state that processing temperature, resistivity, contact resistance, junction leakage, and stress are all lower when using cobalt silicide instead of titanium silicide. However, they report that the difficulty in implementing cobalt silicide in a manufacturing environment has been due to the inability to repeatedly avoid unwanted cobalt silicide overgrowth on the oxide spacers (which can result in electrical shorting) while simultaneously forming thick and uniform cobalt silicide. They reported that the problem of cobalt silicide overgrowth on the oxide portions of the integrated circuit structure could be eliminated by the reactive sputtering of a capping layer of titanium nitride over the layer of cobalt prior to the annealing step to form cobalt silicide.
A later article by Yamazaki et al., entitled "21 psec switching 0.1 .mu.m-CMOS at room temperature using high performance Co salicide process", published on pages 906-908 of IDEM 93, reports that in conventional cobalt salicide (self-aligned silicide), the gate sheet resistance increased below a 1.0 .mu.m gate length because the cobalt layer was oxidized during the first silicidation annealing. They reported that the use of a titanium nitride capping layer over the cobalt salicide effectively avoided the oxidation and drastically improved the gate length dependence of the gate sheet resistance, resulting in the achievement of a gate delay of 21 ps for a 0.1 .mu.m gate length and 19 ps for a 0.075 .mu.m gate length.
It has also been proposed to provide a capping layer of titanium over the cobalt layer prior to the silicidation step. Wang et al., in an article entitled "New CoSi.sub.2 SALICIDE Technology for 0.1 .mu.m Processes and Below", published on pages 17 and 18 of the 1995 Symposium on VLSI Technology Digest of Technical Papers, report that the use of titanium over cobalt in the formation of cobalt silicide provides a much smoother CoSi.sub.2 /poly interface than the conventional process with less sensitivity to pre-sputtering surface conditions and annealing conditions. They also indicate, however, that it is difficult to form thin CoSi.sub.2 on a sub-0.1 .mu.m poly-Si runner using the conventional process, but that the use of a thin titanium capping layer improves both the formation and thermal stability of sub-0.1 .mu.m CoSi.sub.2 /Poly stacks.
However, it would be desirable to provide a process capable of forming shallow source/drain regions of an MOS device in a semiconductor substrate, as well as to form the doped polysilicon gate electrode, by forming cobalt silicide contacts of uniform thickness, and then implanting the cobalt silicide contacts, followed by subsequent annealing of the structure to cause the implanted dopant to diffuse from the cobalt silicide into either the underlying substrate (to form the desired shallow source/drain regions therein), or into the underlying polysilicon gate electrode (to provide the desired conductivity of the polysilicon gate electrode).